1. Field of the Invention
The invention relates to a direct memory access (DMA) system and method, particularly to a DMA system and a DMA method having improved transmission efficiency and high expandability.
2. Description of the Related Art
Direct memory access (DMA) allows direct data transfer between a peripheral device and a memory without the participation of a processor like CPU. The large amount of data transfer between the peripheral device and the memory by way of direct memory access (DMA) does not need any interrupt service from an interrupt service routine and is completed via hardware. Therefore, it would save much time for a processor to execute programs.
As shown in FIG. 1, a DMA controller 11 is considered as a controller that can connect the internal and external memories with the peripheral devices 21, 22, 23, and 24 having DMA capability together via a set of special-purpose buses 12. As data transmission is initialized, after a device driver sets the addresses and counting registers of DMA channels and the direction of data transmission, the DMA hardware is instructed to start the transmission operation. As the transmission operation is finished, the device will notify the CPU 13 by issuing an interrupt. In other words, a conventional DMA operation includes reading and writing operations. Since the bus 12 allows only one of the peripheral devices 21, 22, 23, and 24 to access data during the same period of time, the transmission efficiency of the whole DMA system is lowered in case the data are not ready or the peripheral devices are busy.
Another DMA configuration is shown in FIG. 2 where the peripheral devices 21, 22, 23, and 24 are connected to the DMA controller 11′ via their respective buses 12 to promote the transmission efficiency of the whole DMA system. However, according to the DMA configuration shown in FIG. 2, during data transmission, it is difficult for the peripheral devices 21, 22, 23, and 24 to share the same buffer memory for temporary storage. Thus, in the hardware design for such configuration, buffer memories must be provided for the peripheral devices 21, 22, 23, and 24 individually to occupy considerable chip areas. In addition, such DMA configuration may result in low re-utilization of circuits to increase the number of buses as long as the space of buffer memories when more peripheral devices are incorporated therein. Under the circumstance, it becomes even more difficult to modify the hardware design.